最低限の配線でLEDを点滅

ソースコード

クロック設定をいろいろ変えて確認するプログラム

OSC2(Pin10)にFcy(Fosc/2)が出力されるのでオシロで観測できる。

LEDの点滅速度が変わる

LEDを点滅させるための最低限の設定しかやっていません。

OSCCONのNOSCビットによるクロック設定は行っていません。

main.c

//#pragma config FNOSC = FRC            //FRC 7.37MHz
#pragma config FNOSC = FRCPLL       //FRC x PLL
//#pragma config FNOSC = PRI             //Primary OSC (XT, HS, EC)
//#pragma config FNOSC = PRIPLL        //Primary OSC x PLL
//#pragma config FNOSC = SOSC          //Secondary OSC
//#pragma config FNOSC = LPRC          //Low power RC OSC (32,768Hz)
//#pragma config FNOSC = FRCDIV16    //FRC x 1/16
//#pragma config FNOSC = LPRCDIVN    //FRC x 1/FRCDIV

#pragma config IESO = OFF            //Start-up device with user-selected oscillator source
//#pragma config IESO = ON                  //Start-up device with FRC, then automatically switch to user-selected oscillator source when ready

//#pragma config POSCMD = EC            //Primary OSC EC ( - 64MHz)
//#pragma config POSCMD = XT            //Primary OSC XT (3 - 10MHz)
//#pragma config POSCMD = HS            //Primary OSC HS (10 - 40MHz)
#pragma config POSCMD = NONE        //Primary OSC disable

//#pragma config OSCIOFNC = ON        //OSC2 pin has Digital I/O
#pragma config OSCIOFNC = OFF       //OSC2 pin has clock out function(Fosc/2)

//#pragma config FCKSM = CSECME       //Clock switing and Fail-safe Clock Monitor are enable
//#pragma config FCKSM = CSECMD       //Clock switching is enable, Fail safe Clock Monitor is disable
#pragma config FCKSM = CSDCMD        //Clock switing and Fail-safe Clock Monitor are disable

long i;

int main(void) {
    //CLKDIVbits.ROI = 1;              //Interrupts clears the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
    CLKDIVbits.ROI = 0;         //Interrupts have no effect on the DOZEN bit

    //CLKDIVbits.DOZE = 7;          //Fcy/256
    //CLKDIVbits.DOZE = 6;          //Fcy/64
    //CLKDIVbits.DOZE = 5;          //Fcy/32
    //CLKDIVbits.DOZE = 4;          //Fcy/16
    //CLKDIVbits.DOZE = 3;          //Fcy/8(default)
    //CLKDIVbits.DOZE = 2;          //Fcy/4
    //CLKDIVbits.DOZE = 1;          //Fcy/2
    CLKDIVbits.DOZE = 0;        //Fcy/1

    CLKDIVbits.DOZEN = 0;       //disable DOZE
    //CLKDIVbits.DOZEN = 1;         //enable DOZE

    //CLKDIVbits.FRCDIV = 7;        //FRC/256
    //CLKDIVbits.FRCDIV = 6;        //FRC/64
    //CLKDIVbits.FRCDIV = 5;        //FRC/32
    //CLKDIVbits.FRCDIV = 4;        //FRC/168
    //CLKDIVbits.FRCDIV = 3;        //FRC/8
    //CLKDIVbits.FRCDIV = 2;        //FRC/4
    //CLKDIVbits.FRCDIV = 1;        //FRC/2
    CLKDIVbits.FRCDIV = 0;      //FRC/1(default)

    //CLKDIVbits.PLLPRE = n;        //input/(n + 2) n = 0 - 31
    //CLKDIVbits.PLLPRE = 31;       //input/33
    //CLKDIVbits.PLLPRE = 1;        //input/3
    CLKDIVbits.PLLPRE = 0;      //input/2(default)

    //CLKDIVbits.PLLPOST = 3;      //output/8
    CLKDIVbits.PLLPOST = 1;     //output/4(default)
    //CLKDIVbits.PLLPOST = 0;      //output/2

    //PLLFBDbits.PLLDIV = n;        //x (n + 2) n = 0 - 511
    //PLLFBDbits.PLLDIV = 511;     //x 513
    PLLFBDbits.PLLDIV = 48;       //x 50(default)
    //PLLFBDbits.PLLDIV = 1;        //x 3
    //PLLFBDbits.PLLDIV = 0;        //x 2

    AD1PCFGL = 0xFFFF;          //All Digital

    TRISBbits.TRISB5 = 0;       //RB5(LED)

    /*
     * Fcy = ((OSC x M) / (N1 x N2)) / 2 = ((OSC x PLLDIV) / (PLLPRE x PLLPOST)) / 2
     * e.g. OSC = FRC(7.37MHz) PLL50逓倍　PLLプリスケーラ 2分周 PLLポストスケーラ 4分周
     * Fcy = ((FRC / FRCDIV x M) / (N1 x N2)) / 2 = ((FRC / FRCDIV x PLLDIV) / (PLLPRE x PLLPOST)) / 2
     * FNOSC = FRCPLL
     * FRCDIV = 1
     * PLLDIV = 50
     * PLLPRE = 2
     * PLLPOST = 4
     * Fcy = ((7.37 / 1 x 50) / (2 x 4)) / 2 = 23.03MHz

     * FcyはさらにDOZEで分周できる
     */

    while (1) {
        LATBbits.LATB5 = 1;     //LED ON
        for (i = 0; i < 100000; i++) {
        }
        LATBbits.LATB5 = 0;     //LED OFF
        for (i = 0; i < 100000; i++) {
        }
    };
}

(JF1VRR)